1. Field of the Invention
The invention relates in general to virtual ground memory and more particularly to a memory with low pre-charge loading.
2. Description of the Related Art
Referring to FIG. 1, a conventional virtual ground memory 100 is shown. The conventional virtual ground memory 100 includes a number of memory cells M, a number of metal lines MBL, a number of word lines WL, and a number of select lines BO and BE. Two adjacent metal lines are coupled to two ends of the corresponding memory cell, and the word lines are used for controlling the memory cells.
When a memory cell, for example M71, is to be read, sense amplifier SA1 is coupled to the metal line MBL3 and the metal lines MBL4 is coupled to a ground level. After word line WL1 and select lines BO2 and BE2 are enabled and transistors BSO4 and BSE4 are turned on, the sense amplifier SA charges the end A of memory cell M71 to a high voltage and current I is generated to flow through memory cell M71. Since low current flows through the memory cell with high threshold voltage which stores data 0 and large current flows through the memory cell with low threshold voltage which stores data 1 when a high voltage is applied across the memory cell, the sense amplifier SA read the data stored in memory cell M71 by sensing the amount of current I.
When the word line WL1 is enabled, the memory cells in the same row that are controlled by word line WL1 are all turned on. In order to accelerate the sense amplifier SA to charge the end A of memory cell M71 to the high voltage, pre-charge units are applied to pre-charge all of the memory cells in the left side of the memory cell M71 to the high voltage. Because the amount of memory cells that should be pre-charged is quite large, it is necessary to use at least two pre-charge units PC1 and PC2 to perform pre-charge operation. The metal MBL1 coupled to pre-charge unit PC1 is regarded as a shield of the sense amplifier SA to almost isolate the memory cells in the left side of the metal line MBL1 from the sense amplifier SA. Namely, memory cells in the right side of metal line MBL3 are charged by sense amplifier SA, memory cells between the metal lines MBL2 and MBL3 are charged by sense amplifier SA and pre-charge unit PC2, and memory cells in the left side of metal line MBL1 are charged by pre-charge unit PC2 instead of sense amplifier SA. Therefore, the rate of charging the end A of memory cell M71 to the high voltage by the sense amplifier SA is increased.
However, most of the metal lines in the left side of the metal line MBL1 coupled to pre-charge PC1 are floating, that is, virtual grounded, which conduce a large effective capacitive loading. Moreover, the effective capacitive loading of the pre-charge unit PC1 varies with the position of the memory cell which is to be read. Therefore, pre-charge unit PC1 and PC2 consume extra power to perform pre-charging, and the amount of capacitive loading is also difficult to control.